Field of the Invention
The present invention concerns a process for the manufacture of a high-frequency junction vertical field-effect transistor. It concerns more particularly a transistor of this type comprising a grid constituted of parallel pins of a second type of conductivity embedded or implanted in the upper surface of a subtrate of a first type of conductivity. The upper surface of the subtrate is integral with a source electrode. The lower surface is integral with a drain electrode and a grid contact is provided at the ends of the embedded pins or bars.
The first vertical junction field-effect transistors have, to the applicant's knowledge, been described in French patent published under No. 1.163.241 filed Dec. 10, 1956 by Stanislas Teszner. Since this first description of a vertical field-effect transistor, numerous structures have been described to allow the miniaturization of vertical field-effect transistors and/or the decrease of the access resistance to the grid.
One object of the present invention is to provide a manufacturing process allowing to achieve a particularly miniaturized structure while avoiding the need for steps taking place at high temperature so as to prevent an extension by diffusion of the embedded grid zones.
To achieve this object as well as others, the present invention provides a process for manufacturing a high frequency vertical junction field effect transistor comprising an embedded grid constituted by parallel bars comprising steps consisting of: successively depositing on a silicon substrate of a first type of conductivity silicon oxide layers of a first thickness, silicon nitride and resin layers, and in successively attacking these layers according to an arrangement of parallel bars; implanting a doping impurity of the second type of conductivity masked by the three above layers with an energy such that it is implanted at a certain depth in the substrate, then in removing the resin; in causing to grow at low temperature, for example under high pressure, an oxide layer on the bare silicon, this oxide layer having a second thickness more important than the first and contacting the implanted zone; exposing the ends of the bars of the second type of conductivity, removing the silicon nitride and attacking the silicon oxide on a thickness corresponding to the first thickness; depositing a layer of polycrystalline silicon and separating this layer into two zones of which one, in contact with the substrate zones of the first type of conductivity, is doped according to the first type of conductivity and the other, in contact with the ends of the bars of the second type of conductivity is doped according to this second type of conductivity.
Other aspects of the present invention reside in the manner in which the polycrystalline silicon layer is divided into two zones and in the manner in which the grid contact is taken with the ends of the implanted bars. These other aspects of the invention will be set out in the following description of particular embodiments of the invention.